A clock generator (or oscillator) is a circuit that produces a timing signal commonly referred to as a clock signal for use in synchronizing a circuit's operations. The basic parts that clock generators share include a resonant circuit or piezoelectric crystal and an amplifier, where the resonant circuit or piezoelectric crystal is often a quartz piezoelectric oscillator, although simpler tank circuits and RC circuits may also be used. The amplifier circuit usually inverts the signal from the oscillator and feeds a portion back into the oscillator's input to maintain an oscillation.
Clock circuits are used for a variety of purposes in circuits on both board level systems and integrated circuit (IC) devices. For example, global clock signals are used to synchronize operation of various circuits across a board or an IC device. More complex digital systems, such microprocessors, microcontroller units (MCUs) and field programmable gate arrays (FPGAs), utilize multiple clock signals at several different frequencies. For example, in some microprocessors, internal circuits are clocked by a first clock signal at a first (higher) clock frequency while input/output (I/O) circuits are clocked by a second (lower) clock signal at a second, different clock frequency. In a MCU system, a single clock source is generally distributed to multiple peripherals/modules, such as to analog-to-digital converters (ADCs), a universal serial bus (USB) controller, and a central processing unit (CPU) each needing a different (frequency) divider factor to provide their different frequency.
Multiple clock generating circuits can be used to generate the multiple clock signals at a plurality of different frequencies. However, systems can use a single clock generating circuit to derive all other clock signals from a first “reference” clock signal. For example, clock dividers functioning as frequency dividers can be used to generate one or more clock signals of lower frequencies from a reference clock signal, say from a frequency fin. Typically, the clock dividers receive fin and divide fin by a set of integers given by 2N using D flip flops for dividing fin by powers of two to generate output clock signals having 2N divided frequencies being fin/2, fin/4, fin/8 . . .